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Index–4
N
Naming conventions 3–1
Nios II
Support 1–2
Using the Nios II IDE 7–15
Non-synthesizable Input block 19–15
Non-synthesizable Output block 19–16
Notation
Binary point location 3–3
Fixed-point 3–2
O
Output block 19–17
P
Packet Format Converter
Avalon-ST 7–22
Parallel Adder Subtractor 15–27
Parallel To Serial block 22–15
Pattern block 17–22
Pipeline depth
display 3–25
Pipelined Adder block 15–29
PLL block 20–2
PLL clocks
device support 3–14
Port data type
display format 3–25
Product block 15–31
Q
Qsys
Interfaces library 7–1
Support 1–2
Quartus II assignments
Adding to block entity names 3–28
Quartus II constraints
Adding to a model 3–24
Quartus II project
Adding a DSP Builder design 2–21
Integration of multiple models 12–5
Quartus II Project Global Assignment block 14–10
Quartus II Project Pinout Assignments block 14–11
R
Rate Change library 20–1
Real-Imag to Complex block 16–14
Reset
Asynchronous 3–17
global 3–17
Resource usage
Analyzing 3–26
Resource Usage block 14–12
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
ROM block 22–17
Round block 19–18
S
Saturate block 19–20
Serial To Parallel block 22–19
Shift Taps block 22–20
Signal Compiler 3–19
Adding to a model 2–17
Enabling SignalTap II options 6–6
License 13–1
Synthesis and compilation flows 3–19
Signal Compiler block 14–13
Signal data type
display format 3–25
SignalTap II
Design flow 6–1
Walkthrough 6–3
SignalTap II logic analyzer 6–1
Features 1–2
Performing logic analysis 6–1
Signal Compiler options 6–6
Trigger conditions 6–7
SignalTap II Logic Analyzer block 14–13
SignalTap II Node block 14–15
Simulation
Setting the Simulink solver 2–3
Using ModelSim 2–18
Using Simulink 2–15
Simulation flow 3–20
Simulation library 21–1
Simulation model
HDL 3–16
Simulink
Comparison with ModelSim 3–23
Integration with 1–2
Solver 3–16
Single Pulse block 17–23
Single-Port RAM block 22–22
Solver
Setting simulation parameters 2–3
SOP Tap block 15–33
SOPC builder
Instantiating your design 7–12
Square Root block 15–35
State machine
Implementing 11–1
State Machine Editor
Walkthrough 11–7
State Machine Editor block 23–1
State Machine Functions library 23–1
State Machine table
Walkthrough 11–2
State Machine Table block 23–3
November 2013 Altera Corporation
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